1. Field of the Invention
The present invention generally relates to methods of producing or fabricating semiconductor devices, and more particularly to a method of producing a semiconductor device having multi-level interconnection structure (or multi-layer wiring structure).
2. Description of the Related Art
As the integration density and the performance of semiconductor devices improve, there are demands to improve the speed of signals transferred via interconnections. The so-called RC delay is one cause of the signal delay. The RC delay is the signal delay that occurs proportionally to a product RC of an interconnect resistance R and a capacitance C between interconnections. In order to reduce the interconnect resistance R, the interconnection material has changed from Al to copper (Cu) which has a lower resistivity. The so-called damascene process has been employed to form the interconnection structure using Cu. The damascene process forms via holes and interconnection grooves in an interlayer insulator layer by dry etching, and fills the Cu material into the via holes and the interconnection grooves by plating.
The dry etching chemically or physically removes the interlayer insulator layer such as a silicon oxide layer. However, the residue (or reaction product) that is generated when removing the interlayer insulator layer adheres on the surfaces of the interconnection grooves and the inner walls of the via holes. In addition, the interlayer insulator layer that is removed by the dry etching and the residue are deposited on the inner walls of a dry etching apparatus. Such deposits cure and become sick when exposed to plasma, and may separate during the dry etching process and become foreign particles that adhere on the wafer surface. Unless such foreign particles including the residue are sufficiently removed by surface cleaning, the interconnect resistance R will increase.
For this reason, the residue is removed by wet cleaning. The wet cleaning combines a chemical process that uses cleaning agents, acids, alkali chemicals and the like, and a physical process, such as the two-fluid cleaning, which causes a physical removal by applying ultrasonic waves or by accelerating and spraying a mist of pure water by nitrogen. In addition, techniques for removing the residue and the like using special-purpose water in which zone or hydrogen is dissolved are proposed in Japanese Laid-Open Patent Applications No. 2004-273961 and No. 2004-096055, for example.
Due to the increased integration density of semiconductor devices, the size of via holes and interconnections has become extremely small. For this reason, if a residue of a resist or the residue of the dry etching remains within the via holes and the interconnection grooves, the interconnect resistance R increases and a disconnection of the interconnection is more easily generated. Hence, there are demands to improve the cleaning performance of the wet cleaning.
On the other hand, in order to reduce the CR delay, proposals have been made to use for the interlayer insulator layer a material having a low permittivity compared to that of the conventionally used silicon oxide. However, the interlayer insulator layer (or low-permittivity layer) made of the material having the low permittivity or, low-k material, has a mechanical strength lower than that of the conventionally used silicon oxide layer, and if the two-fluid cleaning described above is used for the wet etching, the via holes and the interconnection grooves are easily damaged. Therefore, although there are demands to improve the performance of the wet cleaning, it is becoming more difficult to employ a physical cleaning technique having a large impact force, such as the two-fluid cleaning.